(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices, and in particular, to a method of forming a stacked gate insulator in sub-quarter micron MOSFETs.
(2) Description of the Related Art
A MOSFET (metal-oxide-semiconductor field-effect transistor) device of related art is shown in FIG. 1. As described fully in S. Wolf and R. N. Tauber, "Silicon Processing for the VLSI Era," vol. 2, Lattice Press, Sunset Beach, Calif, 1990, pp. 298-300, the device is formed on a substrate which is a silicon wafer (10). Of the key elements of the device, a gate electrode (60) is formed over a gate oxide insulator (50) that separates the former from the semiconductor substrate (10) as shown in FIG. 1. A channel region (40) under gate oxide (50) further separates source (20) and drain (20') regions. The source and drain regions are heavily doped while the channel region is lightly doped with a dopant type opposite to that of the source and drain. Gate (60), source (20) and drain (20') regions are connected to their respective terminals (G), (S), and (D) via conductors (60), (70), and (70') as shown in FIG. 1. Normally, input signal is applied to the gate terminal (G) and the output voltage is developed across the source (S) and drain (D) terminals through which the output current, i.e., drain-source current, I.sub.DS flows. Since the semiconductor is physically separated from the gate electrode by the gate oxide insulating layer (typically, SiO.sub.2), no current flows between the gate electrode and the semiconductor.
As is well known (See Wolf, above), the operation of an MOS transistor involves the application of an input voltage to gate electrode (60), which sets up a transverse electric field in channel region (40) of the device. By varying this transverse electric field, it is possible to modulate the longitudinal conductance of the channel region. Since an electric field controls current flow, such devices are termed field-effect transistors (FETs). They are further described as metal-oxide-semiconductor (MOS) FETs because of the thin SiO.sub.2 layer that separates the gate and substrate. We note for completeness that the active or transistor regions where the transistor action occurs are the channel (40) and the heavily doped source and drain regions (20) and (20'), respectively. Active regions on substrate (10) are separated from each other by passive regions (30) which are formed by growing a thick oxide layer (field oxide).
One of the important desired properties of MOSFETs is high output current drive which is inversely proportional to the thickness of the gate oxide. For this reason, gate oxide thickness has grown smaller with each generation of MOS integrated circuits. The present trend is towards oxide thicknesses less than 5 nanometers (nm) as MOSFETs are being scaled below quarter micron. However, below around 5 nm, there is a finite probability that electrons will pass through the gate oxide by means of a quantum-mechanical tunneling effect. For proper device operation, the tunneling current must be small. This effect, as Wolf cited above points out on p. 315, sets a fundamental lower limit of about 5 nm for the thickness of the gate oxide. Alternative gate dielectric materials, including nitrided oxides, thermal nitrides and tantalum oxide have been explored to mitigate this limitation. Since these materials have a larger dielectric constant than that of SiO.sub.2, they can be made thicker than the latter, while keeping the same capacitance per unit area and hence the same switching speed of the device. In fact, Yoon, et al., in U.S. Pat. No. 5,304,503 teach the substitution of tantalum oxide for conventional oxide-nitride-oxide (ONO) composite as the control gate dielectric for this purpose. Bryant in U.S. Pat. No. 5,668,028, on the other hand, teaches the depositing of a thin nitride layer in the forming of a gate structure comprising an oxide layer, a nitride layer and a polysilicon layer. A different gate insulating layer of a triplex structure is proposed by Hayabuchi in U.S. Pat. No. 5,324,675 where a first oxide layer, an oxidation-resistant layer and a second oxide layer are successively formed on a semiconductor substrate.
In addition to the thickness, there are other gate oxide characteristics that need to be addressed in the manufacture of MOSFETs. High quality SiO.sub.2 films typically break down at electric fields of 5-10 megavolts (MV)/cm. However, breakdown may also occur at smaller electric-field values as a result of process-induced flaws in the gate oxide. Such defects include: metal precipitates on the silicon surface prior to oxide growth; high defect density in the silicon lattice at the substrate surface, e.g., stacking faults and dislocations; pinholes and weak spots created in the gate oxide by particulates; thinning of the oxide during growth; and oxide wearout due to failure mechanism related to hot-electron injection. Furthermore, the Si/SiO.sub.2 interface on the surface of the semiconductor substrate must exhibit sufficiently small collection of different types of charges relating to the reliability of submicron MOSFETs.
Without giving all the details that can be found elsewhere and not to obscure the key points of the present invention, it is sufficient to mention here by name the four types of charges that are associated with Si-SiO.sub.2 interfaces which affect the performance of MOSFETs. They are: fixed oxide charges found within approximately 30.ANG. of the Si-SiO.sub.2 interface; mobile ionic charges which mostly arise from sodium or potassium ions in the oxide layer; interface trapped charges referred to as interface states; and oxide trapped charges due to holes or electrons trapped in the bulk of the oxide. Generally, the occurrence of these charges are not well understood and several models have been proposed to explain them. However, it has been observed in the present state of the manufacturing line that these charge impediments can be reduced substantially by forming different composite structures of gate oxide insulating layers. It is disclosed in the present invention that by replacing the conventional SiO.sub.2 layer with a composite layer of Ta.sub.2 O.sub.5 /oxynitride, charge trapping, interface state generation, and breakdown field distribution, the time-dependent dielectric breakdown (TDDB) of gate oxides and hence the reliability of MOSFET devices can be improved substantially.